5 ei16C552 dual fifo uart and parallel port features ibm pc at and ps/2 compatible dual channel version of ei16c550 with centronics printer interface independent control of transmit, receive, line status and data set interrupts on each channel programmable serial interface characteristics for each channel: -5, 6, 7 or 8 bit characters -even, odd or no parity bit generation and dectection -1, 1.5 or 2 stop bit generation programmable baud rate generator divides clk input by a divisor between 1 and (2 16 -1) tri-state ttl drive capability for bidirectional data bus and control bus on each channel 16 byte fifo for receiver as well as for trans mitter. advanced cmos low power technology with single 5 volt supply description the ei16C552 is an enhanced dual channel version of the ei16c550 universal asynchronous receiver transmitter (uart). the device serves two serial input/output interfaces simultaneously in microcom- puter or microprocessor based systems. each chan- nel performs a serial-to-parallel conversion on data characters received from peripheral devices or modems, and a parallel-to-serial conversion on data characters transmitted by the cpu. the complete status of each channel of the dual uart can be read at any time during functional operation by the cpu. the information obtained includes the type and condition of the transfer operations being performed, and error conditions. in addition to its dual commu- nications interface capabilities, the ei16C552 pro- vides the user with a fully bidirectional parallel data port that fully supports the parallel centronics type printer. the parallel port, together with the two serial ports, provide ibm pc at and ps2 compatible computers with a single device to serve the three system ports. pin configuration 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 sout1 dtr1 rts1 cts1 db0 db1 db2 db3 db4 db5 db6 db7 txrdy0 vcc rts0 dtr0 sout0 int1 int2 slin init afd stb gnd pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 int0 bd0 gnd cts0 rsld0 ri0 dsr0 cs0 a2 a1 a0 iow ior cs2 reset vcc sin0 txrdy1 intslc rxrdy0 rsld1 gnd ri1 dsr1 clk cs1 gnd lptoe ack pe busy slct vcc err sin1 rxrdy1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 ei16C552-cj68 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
6 ei16C552 notes on pin description: 1 ) pin 4 and pin 2 can be used by external crystal oscillator in future versions 2) pin 23 and pin 43 can be used as out20?and out21?respectively in future versions ordering information ei16C552 -cj68 68 pin plcc package life support policy : epic products are not to be used in life support devices without prior written authorization. epic semiconductor inc. retains the right to make changes these specifications at any time, without notice. tri-state is a registered trademark of national semiconductor,inc. ibm pc at and ps2 are trademark s of international business machines. block diagram cts0 dsdr0 rlsd0 r10 sin0 cs0 db0-db7 cts1 dsr1 rlsd1 ri1 sin1 cs1 a0-a2 iow ior reset clk err slct busy pe ack lptoe cs2 uart #1 uart #2 parallel port select and control logic 8 8 8 rts0 dtr0 sout0 int0 txrdy0 rxrdy0* rts1 dtr1 sout1 int1 txrdy1 rxrdy1 bdo pd0-pd7 init afd stb slin int2 8 3
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